>talking with asian friends in the semiconductor industry
>apparently everyone wants to get into hbm right now at the exact same moment
>talking with asian friends in the semiconductor industry
>talking with asian friends in the semiconductor industry
>apparently everyone wants to get into hbm right now at the exact same moment
Everyone has been wanting to get into HBM for years but all of the production is going to HPC chips that cost tens of thousands of dollars.
Its not that all of it is going there from necessity, its just that those are the parts with the best profit margin to justify the interposer and packaging costs
An APU with 8GB or 16GB of HBM3 would be so fine, I would buy that ultrabook so quick.
You'd need an absolutely huge console sized IGP to justify the bandwidth that HBM can provide though, and an IGP that size demands a ton of power. Current 35w TDP chips still perform best when given about 70w max to turbo to. I don't consider that ultrabook worthy personally.
The newest APUs would make good use of it. The biggest limitation for APUs is bandwidth, and this entirely fixes that issue.
>The biggest limitation for APUs is bandwidth
No, its not. Look at any review. Rembrandt and Phoenix Point, both with 15-35w SKUs, perform best when configured with their ultimate package power limit at 70w~. They aren't bandwidth starved with fast LPDDR5. They're power starved.
>more power makes chips perform better
WE HAVE A FUCKING ROCKET SURGEON OVER HERE
>The biggest limitation for APUs is bandwidth
at least for the steam deck it doesn't seem like it https://chipsandcheese.com/2023/03/05/van-gogh-amds-steam-deck-apu/
i though that had improved and only was a firmware limit at the start
no. shut up.
give me a 7W (15W turbo) w HBM and iGPU and then STFU
>Intel still doesn't make a 1p4e256eu chip with 4-8GB HBM2
They really just despise making money.
>wanting poopoopeepee core setup
It makes a difference for a small chip. That's four cores for running background processes, each of which can be idled or parked when there's nothing for them to do. It's much more efficient than having a second P core sitting around at 2% load running your music player.
>That's four cores for running background processes, each of which can be idled or parked when there's nothing for them to do.
Does parking E cores really do that much? I thought they were in 4 core clusters, so the suggested core config would put them all in the same cluster.
Apple, Intel, Nvidia, AMD, and Fujitsu all use designs with HBM for years already
what are you talking about OP? or is this yet another gpt bot thread
I missed the non-greentext part, but i meant like, hbm for consumer products
If everyones asking for it now i expect to see it heavily implemented in the next 2-4 years
It already was years ago as he said the fury cards were hbm.
packaging tech has matured to the point where it's possible, complex circuits made with chiplets nets better yields, and the distance between circuits is minimized which allows the circuit to be driven as fast as possible.
moreover, performant computer hardware is the story of a hierarchy of memory.
of course everyone is doing it.
are they confusing HBM with MCM?
>hbm
?
High bandwidth memory. In the consumer space only vega 56,64&VII had HBM so far
It offers as the name suggests quite high bandwidth, which can eliviate bottlenecks for devices with more than 15k cores
>everyone wants to get into hbm
I'm using hbm for 5 years now...
>Does parking E cores really do that much?
A parked core should consume virtually no power.
>right now at the exact same moment
so the same story for the last 10 years but no wait for real this time